Image sensors are widely used in digital still cameras, cellular phones, security cameras, medical, automobile, and other applications. Complementary metal-oxide-semiconductor (“CMOS”) technology is used to manufacture low-cost image sensors on silicon substrates. In a large number of image sensors, a photodiode structure called a pinned photodiode is used because of its low-noise performance.
In these photodiode structures, a P+ type doped pinning layer is ion-implanted at or just below the silicon surface adjacent to a transfer gate. An N-type photosensitive region is ion-implanted deeper into a P-type doped silicon substrate, also adjacent to the transfer gate. The N-type doped layer is the buried layer that stores charge away from the surface region where defects typically reside. The purpose of the P+ type pinning layer is to passivate the defects on the photodiode surface. The relative location of the edges of the P+ type doped pinning layer, the N-type doped photosensitive region, and the adjacent transfer gate should be carefully engineered to improve photodiode charge transfer through the transfer gate. This becomes increasingly important as CMOS image sensors (“CIS”) continue to be miniaturized.
As CIS continue to miniaturize, the area of their pixels and principally their photosensitive regions shrink. This results in less capacity of each pixel to intercept light and hold photo-generated charge. Additionally, as backside illuminated (“BSI”) image sensors are introduced their thinned substrates put further constraints on photo-generated charge, especially for longer wavelength light, which can pass through a silicon substrate without being fully absorbed. Although the advance of manufacturing technology facilitates the decrease in minimum allowable CMOS sizes, the reduction of variability of shape placement (i.e., alignment tolerance) has progressed at a slower rate. Image lag often depends on consistent alignment tolerances between the N-type doped photosensitive region, the P+ type pinning layer, and the adjacent transfer gate edge.